The present invention relates to timing analysis of an integrated circuit design, and more specifically, to a programmable clock division methodology with in-context frequency checking.
The fabrication of an integrated circuit or chip includes several steps to finalize a logic design and analysis and physical implementation. The chip may be designed according to a hierarchical design methodology such that the chip is divided into cores or nests, with each core or nest divided into units that are further divided into macros. The logic design and component placement must result in a physical implementation that meets the requirements for the chip with regard to timing, power, noise, and other aspects. To this end, design analysis (e.g., timing analysis, power analysis, noise analysis) is performed at different hierarchical levels and at different stages of design.